It is well known that as digital multipliers are implemented vor very large operand bit sizes, the complexity, speed of operation and size of circuitry become very large problems. These factors are the primary limitations preventing fast, powerful large-scale integrated multipliers from being commonly used. Others have commonly sought to solve the multiplier size problem by reducing the number of additions required to implement a multiplication operation. Recoding of the binary inputs in accordance with a recoding algorithm such as Booth's algorithm, Modified Booth's algorithm or further Modified Booth's algorithm significantly reduces the number of additions required. Recording schemes typically utilize bit pair recoding meaning that two bits of a binary input are grouped together to require only one addition of an input operand, typically labeled "X", rather than an addition for each bit of the input operand. Recoding schemes larger than bit pair recoding have been used but have the associated disadvantage of introducing further complexity. An example of a recoding multiplier which uses four bit recoding is illustrated by Diedrich et al. in U.S. Pat. No. 4,745,570 entitled "Binary Multibit Multiplier". Diedrich et al. teach a multiplier which uses five adder carry chains to perform a sixteen by N multiply, where N is an integer. The Diedrich et al. multiplier uses five bit groupings for the recoders and form the required X3, X5 and X7 "special product" terms of operand "X" before permitting the addition associated with the first recoding to proceed. Therefore, four adder carry delays due to each of the four recoders exist in addition to a carry delay due to the formation of the special product terms. The speed of the multiplier is directly related to the total number of carry delays.